As the use of electronic devices, such as personal computers, continue to increase, it is becoming ever more important to make such devices portable. The usefulness of portable electronic devices, such as notebook computers, is limited by the limited length of time batteries are capable of powering the device before needing to be recharged. This problem has been addressed by attempts to increase battery life and attempts to reduce the rate at which such electronic devices consume power.
Various techniques have been used to reduce power consumption in electronic devices, the nature of which often depends upon the type of power consuming electronic circuits that are in the device. For example, electronic devices, such a notebook computers, typically include dynamic random access memory (“DRAM”) devices that consume a substantial amount of power. As the data storage capacity and operating speeds of DRAMs continues to increase, the power consumed by such devices has continued to increase in a corresponding manner.
A conventional synchronous dynamic random access memory (“SDRAM”) is shown in FIG. 1. The SDRAM 10 includes an address register 12 that receives bank addresses, row addresses and column addresses on an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). Typically, a bank address is received by the address register 12 and is coupled to bank control logic 16 that generates bank control signals, which are described further below. The bank address is normally coupled to the SDRAM 10 along with a row address. The row address is received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to row address latch & decoder circuit 20a–d for each of several banks of memory cell arrays 22a–d, respectively. One of the latch & decoder circuits 20a–d is enabled by one of the control signals from the bank control logic 16 depending on which bank of memory cell arrays 22a–d is selected by the bank address. The selected latch & decoder circuit 20 applies various signals to its respective bank 22 as a function of the row address stored in the latch & decoder circuit 20. These signals include word line voltages that activate respective rows of memory cells in the banks 22. The row address multiplexer 18 also couples row addresses to the row address latch & decoder circuits 20a–d for the purpose of refreshing the memory cells in the banks 22a–d. The row addresses are generated for refresh purposes by a refresh counter 30.
After the bank and row addresses have been applied to the address register 12, a column address is applied to the address register 12. The address register 12 couples the column address to a column address counter/latch circuit 32. The counter/latch circuit 32 stores the column address, and, when operating in a burst mode, generates column addresses that increment from the received column address. In either case, either the stored column address or incrementally increasing column addresses are coupled to column address & decoders 38a–d for the respective banks 22a–d. The column address & decoders 38a–d apply various signals to respective sense amplifiers 40a–d through column interface circuitry 42. The column interface circuitry 42 includes conventional I/O gating circuits, DQM mask logic, read data latches for storing read data from the memory cells in the banks 22 and write drivers for coupling write data to the memory cells in the banks 22.
Data to be read from one of the banks 22a–d are sensed by the respective set of sense amplifiers 40a–d and then stored in the read data latches in the column interface circuitry 42. The data are then coupled to a data output register 44, which applies the read data to a data bus 48. Data to be written to the memory cells in one of the banks 22a–d is coupled from the data bus 48 through a data input register 50 to write drivers in the column interface circuitry 42. The write drivers then couple the data to the memory cells in one of the banks 22a–d. A data mask signal “DQM” is applied to the column interface circuitry 42 and the data output register 44 to selectively alter the flow of data into and out of the column interface circuitry 42, such as by selectively masking data to be read from the banks of memory cell arrays 22a–d. 
The above-described operation of the SDRAM 10 is controlled by control logic 56, which includes a command decoder 58 that receives command signals through a command bus 60. These high level command signals, which are typically generated by a memory controller (not shown in FIG. 1), are a clock a chip select signal CS#, a write enable signal WE#, a column address strobe signal CAS#, and a row address strobe signal RAS#, with the “#” designating the signal as active low. Various combinations of these signals are registered as respective commands, such as a read command or a write command. The control logic 56 also receives a clock signal CLK and a clock enable signal CKE#, which cause the SDRAM 10 to operate in a synchronous manner. The control logic 56 generates a sequence of control signals responsive to the command signals to carry out the function (e.g., a read or a write) designated by each of the command signals. The control logic 56 also applies signals to the refresh counter 30 to control the operation of the refresh counter 30 during refresh of the memory cells in the banks 22. The control signals generated by the control logic 56, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted. The control logic 56 also includes a mode register 64 that may be programmed by signals coupled through the command bus 60 during initialization of the SDRAM 10. The mode register 64 then generates mode control signals that are used by the control logic 56 to control the operation of the SDRAM 10 in various modes.
A sense amplifier 80 of the type typically used for the sense amplifiers 40a–d in the SDRAM 10 is shown in FIG. 2. As is well-known in the art, one sense amplifier 80 is provided for each column of memory cells in each array of the banks 22a–d, and it is coupled to all of the memory cells in its respective column through complementary digit lines D1, D1*. The sense amplifier 80 includes a pair of cross-coupled PMOS transistors 82, 84 that have their sources coupled to a positive control signal “ACT” and their drains coupled to the digit lines D1, D1*, respectively. The sense amplifier 80 also includes a pair of cross-coupled NMOS transistors 86, 88 that have their sources coupled to a negative control signal “NLAT*” and their drains coupled to the digit lines D1, D1*, respectively.
In operation, when a memory cell is being read, the voltage on one of the digit lines D1, D1* will be slightly greater than the voltage on the other one of digit lines D1, D1*. The ACT signal is then driven high and the NLAT* signal is driven low to enable the sense amplifier 80. The digit line D1, D1* having the lower voltage will turn on the PMOS transistor 82, 84 to a greater extent than the other PMOS transistor 82, 84 is turned on, thereby driving the digit line D1, D1* having the higher voltage high to a greater extent than the other digit line D1, D1* is driven high. Similarly, the digit line D1, D1* having the higher voltage will turn on the NMOS transistor 86, 88 to a greater extent than the other NMOS transistor 86, 88 is turned on, thereby driving the digit line D1, D1* having the lower voltage low to a greater extent than the other digit line D1, D1* is driven low. As a result, after a short delay, the digit line D1, D1* having the slightly greater voltage is driven to the voltage of the ACT signal (which is generally the supply voltage Vcc), and the other digit line D1, D1* is driven to the voltage of the NLAT* signal (which is generally ground potential).
In general, the power consumed by a DRAM, including, of course, the SDRAM 10, increases with both the capacity and the operating speed of the DRAMs. The power consumed by DRAMs is also affected by their operating mode. A DRAM, for example, will generally consume a relatively large amount of power when the memory cells of the DRAM are being refreshed. As is well-known in the art, DRAM memory cells, each of which essentially consists of a capacitor, must be periodically refreshed to retain data stored in the DRAM. Refresh is typically performed by essentially reading data bits from the memory cells in each row of a memory cell array and then writing those same data bits back to the same cells in the row. A relatively large amount of power is consumed when refreshing a DRAM because rows of memory cells in a memory cell array are being actuated in the rapid sequence. Each time a row of memory cells is actuated, a pair of digit lines for each memory cell are switched to complementary voltages and then equilibrated. As a result, DRAM refreshes tends to be particularly power-hungry operations. Further, since refreshing memory cells must be accomplished even when the DRAM is not being used and is thus inactive, the amount of power consumed by refresh is a critical determinant of the amount of power consumed by the DRAM over an extended period. Thus many attempts to reduce power consumption in DRAMs have focused on reducing the rate at which power is consumed during refresh.
Refresh power can, of course, be reduced by reducing the rate at which the memory cells in a DRAM are being refreshed. However, reducing the refresh rate increases the risk of data stored in the DRAM memory cells being lost. More specifically, since, as mentioned above, DRAM memory cells are essentially capacitors, charge inherently leaks from the memory cell capacitors generally either through the capacitors themselves or through respective access transistors coupled to the memory cell capacitors. In either case, charge leaking from the capacitors can change the value of a data bit stored in the memory cell over time. However, current leaks from DRAM memory cells at varying rates. Some memory cell capacitors are essentially short-circuited and are thus incapable of storing charge indicative of a data bit. These defective memory cells can be detected during production testing, and can then be repaired by substituting non-defective memory cells using conventional redundancy circuitry. On the other hand, current leaks from most DRAM memory cells at much slower rates that span a wide range. A DRAM refresh rate is chosen to ensure that all but a few memory cells can store data bits without data loss. This refresh rate is typically once every 64 ms. The memory cells that cannot reliably retain data bits at this refresh rate are detected during production testing and replaced by redundant memory cells. However, refreshing memory cells at a rate that is needed to allow all but the leakiest memory cells to retain data bits actually refreshes the overwhelming majority of the memory cells at a rate that is far higher than the rate needed for these memory cells to retain data bits. As a result, typically used refresh rates cause significantly more power to be consumed than is needed to avoid data loss in most of the memory cells.
Although memory cells that cannot reliably retain data are replaced by redundant memory cells during production testing, the rate of current leakage from DRAM memory cells can change after production testing. In fact, the rate of current leakage can change both as a matter of time and from subsequent production steps, such as in packaging DRAM chips. Current leakage, and hence the rate of data loss, can also be effected by environmental factors, such as the temperature of DRAMs. Therefore, despite production testing and repair, a few memory cells may be unable to retain stored data bits at normal refresh rates or during extended refresh if in low-power operation. In some cases, DRAMs that are unable to retain data during refresh can be detected during post-production testing, such as when memory cells become excessively leaky during packaging. The devices are then discarded, thereby reducing the manufacturing yield of the DRAMs. However, there is no solution for memory cells become excessively leaky during use because conventional DRAMs do not include any means for detecting memory cells that have become excessively leaky. Therefore, conventional DRAMs do not include any means to compensate for memory cells that have become excessively leaky, which could be used to prevent data loss.
One technique that has been used to reduce prevent data errors during refresh is to generate an error correcting code “ECC” from each item of data that is to be written to a DRAM, and to store the ECC along with the write data. When the stored data are to be read from the DRAM, the ECC is read and used to determine if the read data are in error. If the error occurs in less than a specific number of bits, the ECC can be used to correct the read data. Although the use of ECCs can significantly improve the reliability of data stored in the DRAMs, this technique requires that a significant portion of the DRAM storage capacity be used to store the ECCs, thus effectively reducing the storage capacity of the DRAM. ECC typically also slows memory write performance as the memory controller must first read, then merge, then write data to memory on any partial word write to memory. ECC also typically imposes a penalty of extra signal lines between memory and memory controller.
There is therefore a need for a method and system that detects DRAM memory cells that have become excessively leaky after production, and that adjusts the rate at which such memory cells are refreshed to prevent data loss while avoiding excessive refreshes of DRAM memory cells that do not suffer from leakage problems.